Efuses are widely used to prevent current from running away when an apparatus with bulk input capacitors (e.g. a removable PC card) is plugged into a live power supply. Generally, the Efuse is composed of a MOSFET coupled between the power supply and the apparatus, and a corresponding control circuit. At the very beginning of a plug-in event, the MOSFET is off and there is no current flowing through it. Then the gate-source voltage of the MOSFET ramps up slowly, and the current flowing through the MOSFET increases accordingly to charge the output voltage applied to the apparatus up to the input voltage provided by the power supply. This is so called startup period.
In high current applications such as servers and telecom equipments, the Efuse has to handle a large current. Hence, users need to use several MOSFETs (M1˜Mn) in parallel, such as shown in FIG. 1. This topology works well in steady state (when the startup has been finished and all the MOSFETS fully turn on), since the on-resistance of the MOSFET has a positive temperature co-efficiency which allows the plurality of MOSFETs to balance their current automatically. However, the story becomes entirely different in the startup period. As gate terminals of M1˜Mn are tied together and powered by an Efuse controller shown in FIG. 1, the gate-source voltage of all the MOSFETs would ramp up in the same manner. If there is any variation at on-thresholds of these MOSFETs, a MOSFET with lower on-threshold will turn on earlier than the other ones, which will induce excessive stress on this MOSFET and probably cause it to be damaged, especially at high temperature. The current mismatch waveforms are shown in FIG. 2, wherein Ids indicates the current flowing through the MOSFET, Vth indicates the on-threshold and Vgs indicates the gate-source voltage.